PAGE: 4/19
2-5-2.
INTEL I80-TYPE PARALLEL INTERFACE TIMING
(See Fig. 3 and 4)
Table-6
Item
Symbol
Min.
Max.
Unit
RS Setup Time
tRSS
10
?
ns
RS Hold Time
tRSH
10
?
ns
Input Signal Fall Time
tf
?
15
ns
Input Signal Rise Time
tr
?
15
ns
WR/ Pulse Width Low
tWRL
30
?
ns
WR/ Pulse Width High
tWRH
100
?
ns
Write Data Setup Time
tDSi
30
?
ns
Write Data Hold Time
tDHi
10
?
ns
WR/ Cycle Time
tCYCWR
166
?
ns
RD/Cycle Time
tCYCRD
166
?
ns
RD/ Pulse Width Low
tRDL
70
?
ns
RD/ Pulse Width High
tRDH
70
?
ns
Read Data Delay Time
tDDi
?
70
ns
Read Data Hold Time
tDHRi
5 50
ns
Note: All timing is specified using 20% and 80% of Vcc as the reference points.
Fig. 3.
Intel
I80-Type Parallel Interface Write Cycle Timing
DB0-DB7
tf
tOHi
tr
tRSH
tRSS
tDSi
tCYCWR
WR/
RS
tWRL
tWRH
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